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copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. 5v to 12v supply voltage, 8-pin, synchronous buck pwm controller operating with single 5~12v supply voltage or two supply voltages drive dual low cost n-channel mosfets - adaptive shoot-through protection built-in feedback compensation - voltage-mode pwm control - 0~100% duty ratio - fast transient response 2% 0.8v reference - over line, load regulation, and operating temperature programmable over-current protection - using r ds(on) of low-side mosfet hiccup-mode under-voltage protection 118% over-voltage protection adjustable output voltage small converter size - 300khz constant switching frequency - small sop-8 package built-in digital soft-start shutdown control using an external mosfet lead free and green devices available (rohs compliant) features applications general description the apw7120 is a fixed 300khz frequency, voltage mode, and synchronous pwm controller. the device drives two low cost n-channel mosfets and is de- signed to work with single 5~12v or two supply voltage(s), providing excellent regulation for load transients. the apw7120 integrates controls, monitoring, and protection functions into a single 8-pin package to provide a low cost and perfect power solution. a power-on-reset (por) circuit monitors the vcc supply voltage to prevent wrong logic controls. an internal 0.8v reference provides low output voltage down to 0.8v for further applications. an built-in digital soft-start with fixed soft-start interval prevents the output voltage from overshoot as well as limits the input current. the controller s over-current protection monitors the output current by using the voltage drop across the low-side mosfet s r ds(on) , eliminating the need of a current sensing resistor. additional under voltage and over voltage protections monitor the voltage on fb pin for short-circuit and over-voltage protections. the over-current protection cycles the soft-start function until 4 over-current events are counted. pulling and holding the voltage on ocset pin below 0.15v with an open drain device shuts down the controller. pin configuration 1 2 3 4 8 7 6 5 phase ocset fb vcc boot ugate gnd lgate sop-8 motherboard graphics card high current, up to 20a, dc-dc converters
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 2 ordering and marking information apw7120 handling code temperature range package code package code k : sop-8 operating ambient temperature range e : -20 to 70 c handling code tr : tape & reel assembly material l : lead free device g : halogen and lead free device apw7120 k : apw7120 xxxxx xxxxx - date code assembly material note : anpec lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with rohs. anpec lead-free products meet or exceed the lead-free requirements of ipc/jedec j-std- 020c for msl classification at lead-free peak reflow temperature. anpec defines green to mean lead-free (rohs compliant) and halogen free (br or cl does not exceed 900ppm by weight in homogeneous material and total of br and cl does not exceed 1500ppm by weight). symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) -0.3 ~ 16 v v boot boot voltage (boot to phase) -0.3 ~ 16 v ugate voltage (ugate to phase) <400ns pulse width >400ns pulse width -5 ~ v boot +0.3 -0.3 ~ v boot +0.3 v lgate voltage (lgate to gnd) <400ns pulse width >400ns pulse width -5 ~ v cc +0.3 -0.3 ~ v cc +0.3 v phase voltage (phase to gnd) <400ns pulse width >400ns pulse width -10 ~ 30 -3 ~ 16 v v i/o input voltage (ocset, fb to gnd) -0.3 ~ 7 v maximum junction temperature 150 o c t stg storage temperature -65 ~ 150 o c t sdr maximum lead soldering temperature, 10 seconds 260 o c note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings (note 1) symbol parameter typical value unit q ja junction-to-ambient resistance in free air (note 2) 160 o c/w note 2: q ja is measured with the component mounted on a high effective thermal conductivity test board in free air. thermal characteristics
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 3 symbol parameter range unit v cc vcc supply voltage 4.5 ~ 13.2 v v out converter output voltage 0.8 ~ 80%v in v v in converter input voltage 2.2 ~ 13.2 v i out converter output current 0 ~ 20 a t a ambient temperature -20 ~ 70 o c t j junction temperature -20 ~ 125 o c note 3: please refer to the typical application circuit. recommended operating conditions (note 3) electrical characteristics unless otherswise specified, these specifications apply over v cc = 12v, v boot = 12v and t a = -20 ~ 70 o c. typical values are at t a = 25 o c. apw7120 symbol parameter test conditions min. typ. max. unit supply current i vcc vcc nominal supply current ugate and lgate open - 2.1 6 ma vcc shutdown supply current - 1.5 4 ma power-on-reset rising vcc threshold 3.8 4.1 4.4 v hysteresis 0.1 0.45 0.6 v oscillator f osc free running frequency 250 300 350 khz d v osc ramp amplitude - 1.5 - v p-p reference voltage v ref reference voltage measured at fb pin - 0.8 - v t a =25 c -0.75 - +0.75 accuracy t a =-20~70 c, v cc =5v ~ 12v -1.5 - +1.5 % line regulation v cc =5v ~ 12v - 0.05 +0.3 % error amplifier dc gain - 86 - db f p1 first pole frequency - 0.4 - hz f z zero frequency - 0.4 - khz f p2 second pole frequency - 430 - khz average ugate duty range 0 - 85 % fb input current - - 0.1 m a
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 4 apw7120 symbol parameter test conditions min. typ. max. unit pwm controller gate drivers ugate source v boot-phase =12v, v ugate-phase =6v 1.0 2.0 - a ugate sink v boot-phase =12v, v ugate-phase =1v - 3.5 7 w lgate source v cc =12v, v lgate =6v 1.0 1.9 - a lgate sink v cc =12v, v lgate =1v - 2.6 5 w t d dead-time guaranteed by design - 40 100 ns protections i ocset ocset current source v phase =0v, normal operation 35 40 45 m a over-current reference voltage t a =-20~70 c 0.37 0.4 0.43 v u vfb fb under-voltage threshold v fb falling 62 67 72 % fb under-voltage hysteresis - 45 - mv over-voltage threshold v fb rising 114 118 122 % soft-start and shutdown t ss soft-start interval 2 3.8 5 ms ocset shutdown threshold falling v ocset 0.1 0.15 0.3 v ocset shutdown hysteresis - 40 - mv electrical characteristics (cont.) unless otherswise specified, these specifications apply over v cc = 12v, v boot = 12v and t a = -20 ~ 70 o c. typical values are at t a = 25 o c.
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 5 function pin description boot (pin 1) this pin provides ground referenced bias voltage to the high-side mosfet driver. a bootstrap circuit with a diode connected to 5~12v is used to create a voltage suitable to drive a logic-level n-channel mosfet. ugate (pin 2) connect this pin to the high-side n-channel mosfet s gate. this pin provides gate drive for the high-side mosfet. gnd (pin 3) the gnd terminal provides return path for the ic s bias current and the low-side mosfet driver s pull-low current. connect the pin to the system ground via very low impedance layout on pcbs. lgate (pin 4) connect this pin to the low-side n-channel mosfet s gate. this pin provides gate drive for the low-side mosfet. vcc (pin 5) connect this pin to a 5~12v supply voltage. this pin provides bias supply for the control circuitry and the low-side mosfet driver. the voltage at this pin is monitored for the power-on-reset (por) purpose. fb (pin 6) this pin is the inverting input of the internal gm amplifier. connect this pin to the output (v out ) of the converter via an external resistor divider for closed-loop operation. the output voltage set by the resistor divider is deter- mined using the following formula : where r1 is the resistor connected from v out to fb , and r2 is the resistor connected from fb to gnd. the fb pin is also monitored for under and over-voltage events. ocset (pin 7) the ocset is a dual-function input pin for over- current protection and shutdown control. connect a resistor (r ocset ) from this pin to the drain of the low- side mosfet. this resistor, an internal 40 m a current source (i ocset ), and the mosfet s on-resistance (r dson ) set the converter over-current trip level (i peak ) according to the following formula: pulling and holding this pin below 0.15v with an open drain device, with very low parasitic capacitor, shuts down the ic with floating output and also resets the over-current counter. releasing ocset pin initiates a new soft-start and the converter works again. phase (pin 8) the pin provides return path for the high-side mosfet driver s pull-low current. connect this pin to the high- side mosfet s source. (v) ) r2 r1 1 ( 0.8v v out + = (a) r 0.4v - r a 40 i dson ocset peak =
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 6 block diagram vcc power-on- reset vcc ocset ugate lgate oscillator gate control v ref 0.8v soft-start and fault logic f osc 300khz phase gm amplifier fb pwm inhibit 40ua comp 67%v ref uv gnd por soft-start oc boot regulator 3vcc ov 118%v ref 3vcc 0.4v 0.15v enable 2.5v application circuit c3, c4 : 820 m f/16v , esr=25 m w c6, c7 : 1000 m f/6.3v, esr=30 m w v in +5/12v v out 1.8v/15a c5 1uf c3, c4 820uf x2 c6, c7 1000uf x2 l2 1.5uh q1 apm2512 ugate lgate 4 boot 1 gnd 3 vcc 5 phase 8 q2 apm2512 c1 1uf 2 u1 apw7120 fb 6 ocset 7 r2 1.2k c2 0.1uf q3 2n7002 shutdown r4 2.2 l1 1uh r5 +5v/12v c8 0.1uf r1 1.5k r3 200 d1 1n4148 v bias
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 7 35 36 37 38 39 40 41 42 43 44 45 -50-250255075100125150 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 -50-250255075100125150 250 260 270 280 290 300 310 320 330 340 350 -50-250255075100125150 0.788 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 0.810 0.812 -50-250255075100125150 typical operating characteristics junction temperature ( o c) reference voltage vs junction temperature r e f e r e n c e v o l t a g e , v r e f ( v ) switching frequency vs junction temperature junction temperature ( o c) s w i t c h i n g f r e q u e n c y , f o s c ( k h z ) ocset current vs junction temperaturevcc por threshold voltage vs junction temperature junction temperature ( o c) o c s e t c u r r e n t , i o c s e t ( m a ) junction temperature ( o c) v c c p o r t h r e s h o l d v o l t a g e ( v ) rising v cc rising v cc falling v cc falling v cc
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 8 0.10 0.12 0.14 0.16 0.18 0.20 -50-250255075100125150 typical operating characteristics (cont.) junction temperature ( o c) ocset shutdown threshold voltage vs junction temperature o c s e t s h u t d o w n t h r e s h o l d v o l t a g e ( v ) operating waveforms (refer to the typical application circuit, v bais =v in =+12v supplied by an atx power supply) 1. load transient response : i out = 0a -> 15a -> 0a - i out slew rate = 15a/ m s ch1 : v out , 100mv/div, dc, offset = 1.8v ch2 : i out , 10a/div ch3 : v ugate , 20v/div, dc time : 2 m s/div bw = 20 mhz ch1 : v out , 100mv/div, dc, offset = 1.8v ch2 : i out , 10a/div ch3 : v ugate , 20v/div, dc time : 50 m s/div bw = 20 mhz ch1 : v out , 100mv/div, dc, offset = 1.8v ch2 : i out , 10a/div ch3 : v ugate , 20v/div, dc time : 2 m s/div bw = 20 mhz i out = 0a -> 15ai out = 0a -> 15a -> 0ai out = 15a -> 0a falling v ocset falling v ocset 1 1 3 3 2 2 v out v ugate i out 1 1 3 3 2 2 v out =1.8v v out v ugate i out 15a 15a 0a 0a 1 1 3 3 2 2 v out v ugate i out
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 9 operating waveforms (cont.) 2. ugate and lgate switching waveforms rising v ugate ch1 : v ugate , 5v/div, dc time : 20ns/div ch2 : v lgate , 2v/div, dc bw = 500 mhz falling v ugate ch1 : v ugate , 5v/div, dc time : 20ns/div ch2 : v lgate , 2v/div, dc bw = 500 mhz 3. powering on / off powering on powering off ch1 : v cc , 2v/div, dc ch3 : i l , 10a/div, dc bw = 20 mhz ch2 : v out , 1v/div, dc time : 10ms/div v ugate 1,2 1,2 i out = 15a v lgate 1,2 1,2 v ugate v lgate 2 2 v cc i l v out 2 2 v cc i l v out (refer to the typical application circuit, v bias =v in =+12v supplied by an atx power supply) v cc =v in =5v r l =0.12 w 1 1 3 3 v cc =v in =5v r l =0.12 w 1 1 3 3 ch1 : v cc , 2v/div, dc ch3 : i l , 10a/div, dc bw = 20 mhz ch2 : v out , 1v/div, dc time : 5ms/div
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 10 3. powering on / off (cont.) powering on powering off 2 2 v cc i l v out 2 2 v cc i l v out 1 1 3 3 1 1 3 3 operating waveforms (cont.) (refer to the typical application circuit, v bias =v in =+12v supplied by an atx power supply) v cc =v in =12v r l =0.12 w 4. enabling and shutting down enabling by releasing ocset pin ch1 : v out , 1v/div, dc ch3 : v ocset , 2v/div, dc bw = 20 mhz ch2 : v ugate , 20v/div, dc time : 2ms/div shutting down by pulling ocset low ch1 : v out , 1v/div, dc ch3 : v ocset , 2v/div, dc bw = 20 mhz ch2 : v ugate , 20v/div, dc time : 2ms/div 1 1 3 3 2 2 v out v ugate v ocset i out =2a v out v ugate v ocset 1 1 3 3 2 2 v cc =v in =12v r l =0.12 w ch1 : v cc , 5v/div, dc ch3 : i l , 10a/div, dc bw = 20 mhz ch2 : v out , 1v/div, dc time : 5ms/div ch1 : v cc , 5v/div, dc ch3 : i l , 10a/div, dc bw = 20 mhz ch2 : v out , 1v/div, dc time : 10ms/div
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 11 operating waveforms (cont.) 5. over-current protection no connecting a shutdown mosfet at ocset pin ch1 : v out , 1v/div, dc time : 5ms/div ch2 : i l , 10a/div, dc bw = 20 mhz connecting a shutdown mosfet (2n7002) at ocset pin ch1 : v out , 1v/div, dc time : 5ms/div ch2 : i l , 10a/div, dc bw = 20 mhz i l 1 1 2 2 v out i l 1 1 2 2 v out r ocset =15k apm2512 r ocset =15k apm2512 (refer to the typical application circuit, v bias =v in =+12v supplied by an atx power supply) 6. ocset voltage rc delay ch1 : v ocset , 0.5v/div, dc time : 2 m s/div ch2 : i l , 10a/div, dc bw = 20 mhz ch1 : v ocset , 0.5v/div, dc time : 2 m s/div ch2 : i l , 10a/div, dc bw = 20 mhz v ocset i l c prober =8pf ocp ocp 1,2 1,2 i l ocp ocp 1,2 1,2 v ocset no connecting a shutdown mosfet at ocset pin connecting a shutdown mosfet (2n7002) at ocset pin c prober =8pf c 2n7002 =44pf (measured)
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 12 operating waveforms (cont.) 7. short-circuit test ch1 : v out , 1v/div, dc time : 5ms/div ch2 : i l , 10a/div, dc bw = 20 mhz 1 1 2 2 v out i l uvp ocp ocp ocp ocp shorted by a wire (refer to the typical application circuit, v bias =v in =+12v supplied by an atx power supply) 6. ocset voltage rc delay (cont.) ch1 : v ocset , 0.5v/div, dc time : 2 m s/div ch2 : i l , 10a/div, dc bw = 20 mhz i l v ocset ocp ocp 1,2 1,2 connecting a shutdown mosfet (apm2322) at ocset pin c prober =8pf c apm2322 =89pf (measured) function description power-on-reset (por) the apw7120 monitors the vcc voltage (v cc ) for power-on-reset function, preventing wrong logic operation during powering on. when the vcc voltage is ready, the apw7120 starts a start-up process and then ramps the output voltage up to the target voltage. soft-start the apw7120 has a built-in digital soft-start to control the output voltage rise and limit the current surge at the start-up. during the soft-start, an internal ramp con- nected to the one of the positive inputs of the gm amplifier rises up from 0v to 2v to replace the reference voltage (0.8v) until the ramp voltage reaches the refer- ence voltage. the soft-start interval is about 3.2ms typical, independent of the converter s input and out- put voltages. over-current protection (ocp) the over-current function protects the switching converter against over-current or short-circuit conditions. the controller senses the inductor current by detecting the drain-to-source voltage, product of the inductor s current and the on-resistance, of the low-side mosfet during it s on-state. this method enhances the converter s efficiency and reduces cost by eliminating a current sensing resistor. a resistor (r ocset ), connected from the ocset to the
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 13 low-side mosfet s drain, programs the over-current trip level. an internal 40 m a (typical) current source flowing through the r ocset develops a voltage (v rocset ) across the r ocset . when the v ocset (v rocset + v ds of the low-side mosfet) is less than the internal over- current reference voltage (0.4v, typical), the ic shuts off the converter and then initiates a new soft-start process. after 4 over-current events are counted, the device turns off both high-side and low-side mosfets and the converter s output is latched to be floating. please pay attention to the rc delay effect. it causes the ocp trip level to be the function of the operating duty. the parasitic capacitance, includ- ing the capacitance inside the ocset, external pcb trace capacitance, and the c oss of the shutdown mosfet, must be minimized, especially selecting a shutdown mosfet with very small c oss . the ocp trip level follows the duty to increase a little at low operating duty, but very much at high operating duty, like the rc delay curve. due to load regulation or current-limit, heavy load normally reduces converter s input voltage and increases the power loses. during heavy load, the apw7120 regulates the output voltage by expending the duty. this rises up the ocp trip level at the same time. under-voltage protection (uvp) the under-voltage function monitors the fb voltage (v fb ) to protect the converter against short-circuit conditions. when the v fb falls below the falling uvp threshold (67% v ref ), the apw7120 shuts off the converter. after a preceding delay, which starts at the beginning of the under-voltage shutdown, the apw7120 initiates a new soft-start to resume regulating. the under-voltage protection shuts off and then re-starts the converter repeatedly without function description (cont.) over-current protection (ocp) (cont.) latching. the function is disabled during soft-start process. over-voltage protection (ovp) the over-voltage protection monitors the fb voltage to prevent the output from over-voltage. when the output voltage rises to 118% of the nominal output voltage, the apw7120 turns on the low-side mosfet until the output voltage falls below the ovp threshold, regulating the output voltage around the ovp thresholds. adaptive shoot-through protection the gate driver incorporates adaptive shoot-through protection to high-side and low-side mosfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the falling gate has turned off one mosfet before the other is allowed to rise. during turn-off of the low-side mosfet, the lgate voltage is monitored until it reaches a 1.5v threshold, at which time the ugate is released to rise after a constant delay. during turn-off of the high-side mosfet, the ugate-to-phase voltage is also monitored until it reaches a 1.5v threshold, at which time the lgate is released to rise after a constant delay. shutdown control pulling the ocset voltage below 0.15v by an open drain transistor, shown in typical application circuit, shuts down the apw7120 pwm controller. in shut- down mode, the ugate and lgate are pulled to phase and gnd respectively, the output is floating.
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 14 application information input capacitor selection use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the surge current needed each time high-side mosfet(q1) turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of low-side mosfet(q2). the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current of the bulk input capacitor is calculated as the following equation : (a) d) - (1 d i i out rms = for a through hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. v in v out c in c out l q1 ugate q2 lgate esr i l i out i q1 i cout i out v ugate t=1/f osc i l i q1 i cout i out i i v out dt v out figure 1 buck converter waveforms output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the filtering requirements are the functions of the switching frequency and the ripple current. the output ripple is the sum of the voltages, having phase shift, across the esr and the ideal output capacitor. the peak-to-peak voltage of the esr is calculated as the following equations : the peak-to-peak voltage of the ideal output capacitor is calculated as the following equation : ..(3) .......... (v) esr i v .(2) .......... (a) l f d) - (1 v i (1) . .......... (v) v d v esr osc out in out d = = d = (4) ....... (v) c f 8 i v out osc cout d = d for general applications using bulk capacitors, the d v cout is much smaller than the v esr and can be ignored. therefore, the ac peak-to-peak output volt- age is shown below: the load transient requirements are the functions of .(5) .......... (v) esr i v out d = d
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 15 the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. an aluminum electrolytic capacitor s esr value is re- lated to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter s response time to the load transient. the inductor value determines the converter s ripple current and the ripple voltage, see equations (2) and (5). increasing the value of inductance reduces the ripple current and voltage. however, the large inductance val ues reduce the converter s response time to a load transient. one of the parameters limiting the converter s response application information (cont.) output capacitor selection (cont.) where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. the worst case response time can be either at the application or removal of load. be sure to check both of these equations at the transient load current. these requirements are minimum and maximum output levels for the worst case response time. mosfet selection the apw7120 requires two n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection, and heatsink are the dominant design factors. the power dissipation includes two loss components, conduction loss, and switching loss. the conduction losses are the largest component of power dissipation for both the high-side and the v i l t , v v i l t out tran fall out in tran rise = - = to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the apw7120 will provide either 0% or 85% (average) duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the fol- lowing equations give the approximate response time interval for application and removal of a transient load:
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 16 low-side mosfets. these losses are distributed between the two mosfets according to duty factor (see the equations below). only the high-side mosfet has switching losses, since the low-side mosfets body diode or an external schottky rectifier across the lower mosfet clamps the switching node before the synchronous rectifier turns on. these equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the low-side mosfet s body diode. the gate- charge losses are dissipated by the apw7120 and don t heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the high-side mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal- resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature, and air flow. where : t sw is the switching interval application information (cont.) mosfet selection (cont.) d) - (1 r i p f t v i 2 1 d r i p dson 2 out side - low osc sw in out dson 2 out side - high = + = feedback compensation the figure 2 shows the control system of the apw7120, which consists of an internal voltage-mode pwm modulator, an output l-c filter, a resistor-divider and an internal compensation network. the r and c are the equivalent series resistance(esr) and capaci- tance of the output capacitor; the l is the inductance of the output inductor. r2 r1 v out apw7120 v fb r c 0.8v fb v o l v osc =1.6v driver v phase v in v comp internal compensation network ugate lgate figure 2. apw7120 control system the transfer functions are defined as following : r2 r1 r2 (s) v (s) v a1(s) o fb + = = on) compensati (internal (s) v (s) v a2(s) fb comp = v v (s) v (s) v a3(s) osc in comp phase d = = 1 s c r s c l 1 s c r (s) v (s) v a4(s) 2 phase out + + + = = out cl o fbcompphaseout ofbcompphase v(s) a(s) v(s) v(s)v(s)v(s)v(s) v(s)v(s)v(s)v(s) a1(s)a2(s)a3(s)a4(s) = = = where a1(s) is the transfer function of the resistor- divider, a2(s) is the transfer function of the feedback compensation network, a3(s) is the transfer function of the pwm modulator, a4(s) is the transfer function of the output lc filter, and a cl (s) is the transfer func- tion of the closed-loop control system. refer to figure 3. the pole and zero frequencies of the a1(s), a2(s), a3(s) and a cl (s) are shown or calculated as the fol- lowing equations: ) (f 0.4khz f z za21 = ) (f 430khz f p2 pa21 = lc x 2 1 f pa41,2 p = xrxc 2 1 f za41 p =
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 17 application information (cont.) feedback compensation (cont.) where the f pa21 (or f p2 ) and f za21 (or f z ) are the pole and zero frequencies of the a2(s), the f pa41,2 , and f za41 are the double-pole and zero frequencies of the a4 (s), the v in is the input voltage of the pwm converter and the load resistance of the converter is very large. for good converter stability, the values of the l, c, and r must be selected to meet the following criteria: 1.make sure the double-pole frequency(f pa41,2 ) of the output filter is bigger than the zero frequency (f za21 ) of the internal compensation network. 2. the following equation must be true: 0 1.2 ) c l r 1 log( 2 ) r2 r1 r2 log( ) v v log( osc in > + - + + d 3. the converter crossover frequency (f co ) must be in the range of 10%~30% of minimum f osc of the converter. the f co is calculated by using the following equations: 7 2 ) c l r 1 log( 40 ) r2 r1 r2 log( 20 ) v v log( 20 f at gain osc in za41 + - + + d = osc_min za41 20 fza41 at gain co osc_min f 30% f 10 f f 10% ? ? ? ? ? = 4. the values of l, c, and r selected must meet the equations above over the operaing temperatu- re, voltage, and current ranges. figure 3. converter gain vs. frequency layout consideration in high power switching regulator, a correct layout is important to ensure proper operation of the regulator. in general, interconnecting impedances should be minimized by using short and wide printed circuit traces. signal and power grounds are to be kept sepa- rating and finally combined using ground plane con- struction or single point grounding. figure 4 illustrates the layout, with bold lines indicating high current paths. components along the bold lines should be placed close together. below is a checklist for your layout: 1. begin the layout by placing the power components first. orient the power circuitry to chieve a clean power flow path. if possible, make all the connections on one side of the pcb with wide, copper filled areas. 2. connect the ground of feedback divider directly to the gnd pin of the ic using a dedicated ground trace. 3. the vcc decoupling capacitor should be right next to the vcc and gnd pins. capacitor c boot should be connected as close to the boot and phase pins as possible. -60 -40 -20 0 20 40 60 80 100 1001k10k100k1m10m compensation gain f za41 f pa41,2 frequency (f, hz) g a i n ( d b ) f za21 f pa21 converter gain pwm &filter gain f co 4. minimize the length and increase the width of the trace between ugate/lgate and the gates of the mosfets to reduce the impedance driving the mosfets. 5. use an dedicated trace to connect the r ocset and the drain pad of the low-side mosfet, kevin connection , for accurate current sensing. 6. keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep tracing to these nodes as short as possible. 7. place the decoupling ceramic capacitor c hf near the drain of the high-side mosfet as close as possible. the bulk capacitors c in are also placed near the drain.
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 18 layout consideration (cont.) application information (cont.) 8. place the source of the high-side mosfet and the drain of the low-side mosfet as close as possible. minimizing the impedance with wide lay- out plane between the two pads reduces the volt- age bounce of the node. 9. use a wide power ground plane, with low impedance, to connect the c hf , c in , c out , schottky diode, and the source of the low-side mosfet and to provide a low impedance path between the components for large and high frequency switch- ing currents. v in v out q1 l1 4 8 2 u 1 1 5 c out c in + + apw7120 ugate lgate vcc phase boot c hf q2 figure 4. recommended layout diagram
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 19 package information sop-8 s y m b o l min.max. 1.75 0.10 0.170.25 0.25 a a1 c d e e1 e h l millimeters b 0.310.51 sop-8 0.250.50 0.401.27 min.max. inches 0.069 0.004 0.0120.020 0.0070.010 0.0100.020 0.0160.050 0 0.010 1.27 bsc0.050 bsc a2 1.25 0.049 0 8 0 8 d e e e 1 see view a c b h x 4 5 a a 1 a 2 l view a 0 . 2 5 seating plane gauge plane note: 1. follow jedec ms-012 aa. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension e does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. 3.80 5.80 4.80 4.00 6.20 5.00 0.1890.197 0.2280.244 0.1500.157
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 20 carrier tape & reel dimensions h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 330.0 2.00 50 min. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 min. 20.2 min. 12.0 0.30 1.75 0.10 5.5 0.05 p0 p1 p2 d0 d1 t a0 b0 k0 sop-8 4.0 0.10 8.0 0.10 2.0 0.05 1.5+0.10 -0.00 1.5 min. 0.6+0.00 -0.40 6.40 0.20 5.20 0.20 2.10 0.20 (mm) package type unit quantity sop-8 tape & reel 2500 devices per unit
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 21 t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 t e m p e r a t u r e time critical zone t l to t p test item method description solderability mil-std-883d-2003 245 c, 5 sec holt mil-std-883d-1005.7 1000 hrs bias @125 c pct jesd-22-b, a102 168 hrs, 100 % rh, 121 c tst mil-std-883d-1011.9 -65 c~150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms, 1 tr > 100ma reliability test program profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat - temperature min (tsmin) - temperature max (tsmax) - time (min to max) (ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: - temperature (t l ) - time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak/classification temperature (tp) see table 1 see table 2 time within 5 c of actual peak temperature (tp) 10-30 seconds 20-40 seconds ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note: all temperatures refer to topside of the package. measured on the body surface. classification reflow profiles reflow condition (ir/convection or vpr reflow)
copyright ? anpec electronics corp. rev. a.5 - jun., 2008 apw7120 www.anpec.com.tw 22 table 2. pb-free process C package classification reflow temperatures package thickness volume mm 3 <350 volume mm 3 350-2000 volume mm 3 >2000 <1.6 mm 260 +0 c* 260 +0 c* 260 +0 c* 1.6 mm C 2.5 mm 260 +0 c* 250 +0 c* 245 +0 c* 3 2.5 mm 250 +0 c* 245 +0 c* 245 +0 c* * tolerance: the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means peak reflow temperature +0 c. for example 260 c+0 c) at the rated msl level. customer service anpec electronics corp. head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 2f, no. 11, lane 218, sec 2 jhongsing rd., sindian city city, taipei county 23146, taiwan tel : 886-2-2910-3838 fax : 886-2-2917-3838 table 1. snpb eutectic process C package peak reflow temperatures package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 240 +0/-5 c 225 +0/-5 c 3 2.5 mm 225 +0/-5 c 225 +0/-5 c classification reflow profiles (cont.)

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